FIG. 1 shows an essential part of an example of a conventional sense circuit together with related parts of an erasable programmable read only memory (EPROM). A floating gate transistor Q6 corresponds to a memory cell of the EPROM, and this transistor Q6 receives a word line selection signal X from a word line 10. A node N.sub.3 corresponds to a bit line, and this node N.sub.3 is coupled to a node N.sub.2 which corresponds to a bus line via a transistor Q5. The transistor Q5 receives a bit line selection signal Y. Transistors Q1 and Q2 form an inverter and is used as a bias circuit for feeding back a signal at the node N.sub.2 to a transistor Q4. In order to prevent soft error, the potential at the node N.sub.2 is set to approximately 1 V. Driving transistors Q3 and Q8 form a current mirror circuit. A transistor Q7 acts as a load and flows a current which is approximately 1/2 a cell current that a transistor Q6 flows. A sensed data DATA is output from a terminal 11.
When sensing the data, the bit line selection signal Y is set to a high level to select a single bit line, and thus, a potential at the node N.sub.3 is pulled up from 0 V to 1 V by the bias circuit. Thereafter, the word line selection signal X is set to a high level to select a single word line. For example, when a data is already written into the transistor Q6 (that is, the transistor Q6 is programmed), a current does not flow through the transistor Q6 and the potential at the base of the transistor is at the high level. In other words, the data DATA has the high level, and thus, a low-level data DATA is read out from the terminal 11.
According to the conventional sense circuit, a level fluctuation peculiar to a feedback circuit is generated by the bias circuit when the potential at the node N.sub.3 is pulled up from 0 V to 1 V. For this reason, there is a problem in that the potential at the node N.sub.1 and the potential of the data DATA fluctuate, thereby making a high-speed data read operation difficult. This problem is caused by a slow response of the inverter which is formed by the transistors Q1 and Q2 and a poor convergence of the level fluctuation of the bias circuit in a vicinity of a steady state level (1 V) of the node N.sub.3.